PROJECT TITLE :
CMCS: Current-Mode Clock Synthesis - 2017
In a very high-performance VLSI style, the clock network consumes a vital amount of power. Whereas most existing methodologies use voltage-mode (VM) signaling, these clock distributions lose a tremendous quantity of dynamic power to charge/discharge the large international clock capacitance. New circuit approaches for current-mode (CM) clocking save vital clock power, however have been limited to only symmetric networks, while most application specific integrated circuits have asymmetric clock distributions. In this paper, we have a tendency to propose the first CM clock synthesis (CMCS) methodology to scale back the overall clock network power with low skew. The method can integrate with ancient clock routing followed by transmitter and receiver sizing. We tend to validate the proposed methodology using ISPD 2009 and 2010 industrial benchmarks using an extracted SPICE model distributed in one.4-275.6-mm 2 space and consists of 81-2249 sinks. This methodology saves thirty-nine%-eighty four% average power with similar skew on the benchmarks using 45-nm CMOS technology simulation of clock frequencies range from one-3 GHz. Still, the CMCS methodology takes two.4-9.one× less running time and consumes twenty%-26percent less transistor space compared with synthesized, buffered VM clock distributions.
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