An Optimised 3x3 Shift and Add Multiplier on FPGA - 2017


Shift and add is standard multiplication technique used at most, thanks to its simplest architecture. This simplicity becomes the bottleneck, when its hardware implementation takes additional resources, when implemented on FPGAs. Though FPGA is, taken as an economical implementation tool, but limited resources are the design hurdle observed several times. Optimizations is the manner, opt, to design massive circuits, especially whole system on chip (SOC), or network on chip (NOC) on this device. Therefore several ways of multiplier optimization are found with some modifications in standard strategies along their implementation and testability on FPGA. In this paper, implementation of fastened point finite length three×3 unsigned integer shift and add multiplier is shown, by introducing some changes in procedure. The modified version results in less resource utilizations in terms of Lookup Tables (LUTs) and produce less delay, because of less levels of logics, compared with typical technique.

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