PROJECT TITLE :
Optimization of Constant Matrix Multiplication with Low Power and High Throughput - 2017
Constant matrix multiplication (CMM), i.e., the multiplication of a relentless matrix with a vector, may be a common operation in digital signal processing. It is a generalization of multiple constant multiplication (MCM) where one variable is multiplied by a continuing vector. Like MCM, CMM will be reduced to additions/subtractions and bit shifts. Finding a circuit with minimal variety of add/subtract operations is referred to as the CMM downside. Whereas this results in a discount in circuit space it could be less economical for power consumption or throughput. It's well studied for the MCM downside that a) reducing the adder depth (AD) ends up in a reduced power consumption and b) pipeline resources need to be thought-about during optimization to enhance throughput while not wasting area. This paper addresses the optimization of CMM circuits which considers each adder depth and pipelining for the first time. For that, a heuristic is proposed which evaluates the foremost attractive graph topologies. It is shown that the proposed method requires 12.5p.c less adders with min. AD and thirty eight.5% less pipelined operations. Synthesis results for recent FPGAs show that these reductions additionally translate to superior leads to terms of delay and power consumption compared to the state-of-the-art.
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