Comparative study of 16-order FIR filter design using different multiplication techniques - 2017 PROJECT TITLE :Comparative study of 16-order FIR filter design using different multiplication techniques - 2017ABSTRACT:This study represents planning and implementation of an occasional power and high speed sixteen order FIR filter. To optimise filter area, delay and power, different multiplication techniques like Vedic multiplier, add and shift methodology and Wallace tree (WT) multiplier are used for the multiplication of filter coefficient with filter input. Varied adders such as ripple carry adder, Kogge Stone adder, Brent Kung adder, Ladner Fischer adder and Han Carlson adder are analysed for optimum performance study for additional use in varied multiplication techniques together with barrel shifter. Secondly optimisation of filter space and delay is completed by using add and shift technique for multiplication, although it will increase power dissipation of the filter. To scale back the complexity of filter, coefficients are represented in canonical signed digit illustration as it is more efficient than ancient binary representation. The finite impulse-response (FIR) filter is meant in MATLAB using equiripple method and the identical filter is synthesised on Xilinx Spartan 3E XC3S500E target field-programmable gate array device using Terribly High Speed Integrated Circuit Hardware Description Language (VHDL) subsequently the whole on-chip power is calculated in Vivado2014.four. The comparison of simulation results of all the filters show that FIR filter with WT multiplier is the most effective optimised filter. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest VLSI FPGA MTech Projects An Optimised 3x3 Shift and Add Multiplier on FPGA - 2017 RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing - 2017
