Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing - 2017


Approximate computing is an attractive design methodology to achieve low power, high performance (low delay) and reduced circuit complexity by relaxing the requirement of accuracy. During this paper, approximate Booth multipliers are designed based on approximate radix-four modified Booth encoding (MBE) algorithms and an everyday partial product array that employs an approximate Wallace tree. Two approximate Booth encoders are proposed and analyzed for error-tolerant computing. The error characteristics are analyzed with respect to the so-called approximation factor that's connected to the inexact bit width of the Booth multipliers. Simulation results at 45 nm feature size in CMOS for delay, area and power consumption are also provided. The results show that the proposed sixteen-bit approximate radix-four Booth multipliers with approximate factors of twelve and fourteen are more correct than existing approximate Booth multipliers with moderate power consumption. The proposed R4ABM2 multiplier with an approximation factor of fourteen is the most efficient style when considering both power-delay product and therefore the error metric NMED. Case studies for Image Processing show the validity of the proposed approximate radix-4 Booth multipliers.

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