Graph-Based Transistor Network GenerationMethod for Super gate Design - 2016


Transistor network optimization represents a good method of improving VLSI circuits. This paper proposes a novel technique to automatically generate networks with minimal transistor count, beginning from an irredundant add-of-product expression as the input. The technique is able to deliver each series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and space of CMOS gates. Experimental results demonstrate expected gains compared with related approaches.

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