Design for Testability of Sleep Convention Logic - 2016 PROJECT TITLE : Design for Testability of Sleep Convention Logic - 2016 ABSTRACT: Testability could be a major concern in business for nowadays's advanced system-on-chip design. Style-for-testability (DFT) techniques are essential for any logic vogue, together with asynchronous logic designs so as to reduce the test price. Sleep convention logic (SCL) may be a new promising asynchronous logic style that is based on the a lot of well-known asynchronous logic style NULL convention logic (NCL). In contrast to the NCL, there are currently no style for testability methodologies existing for the SCL. The aim of this paper is to research the various faults within SCL pipelines and propose a scan-based DFT methodology to create the SCL testable. The proposed DFT methodology is then validated through a variety of experiments, showing that the methodology provides a high check coverage (>99%). The complete DFT methodology still as the scan chain and scan cell style are presented. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Design For Testability Logic Design System-On-Chip Asynchronous Circuits Sleep Convention Logic (SCL) Design For Testability (DFT) Multithreshold Null Convention Logic (Mtncl) Null Convention Logic (NCL) Low-Cost and High-Reduction Approaches for Power Droop During Launch-On-Shift Scan-Based Logic BIST - 2016 Computing Seeds for LFSR-Based Test Generation From Non test Cubes - 2016
