Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories - 2016


Error correction code (ECC) and built-in self-repair (BISR) techniques by using redundancies have been widely used for improving the yield and reliability of embedded recollections. The target faults of these 2 schemes are soft errors and permanent (laborious) faults, respectively. In recent works, there also are some techniques integrating ECC and BISR to deal with soft errors and arduous defects simultaneously. However, this will compromise reliability, since a number of the ECC protection capability is employed for repairing single laborious faults. To cure this dilemma, we have a tendency to propose an ECC-enhanced BISR (EBISR) technique, which uses ECC to repair single permanent faults 1st and spares for the remaining faults in the assembly/power-ON test and repair stage. However, techniques are proposed to keep up the original reliability during the online take a look at and repair stage. We additionally propose the corresponding hardware design for the EBISR scheme. A simulator is implemented to guage the hardware overhead (HO), repair rate, reliability, and performance penalty. Experimental results show that the proposed EBISR scheme can improve yield and reliability considerably with negligible HO and performance penalty.

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