A New XOR-Free Approach for Implementation of Convolutional Encoder - 2016


This letter presents a new algorithm to construct an XOR-Free architecture of an influence efficient Convolutional Encoder. Optimization of XOR operators is the most concern while implementing polynomials over GF(2), that consumes a important amount of dynamic power. The proposed approach fully removes the XOR-processing operation of a chosen nonsystematic, feed-forward generator polynomial and reduces the logical operators, thereby the encoding cost. Hardware (HW) implementation of the proposed style uses Scan-solely memory (ROM) with a preprocessed addressing operations to reduce ROM size by nearly fiftyp.c. The results of the new architecture reduce the dynamic power up to 21.4percent and HW cost up to 15percent with lesser design complexity as compared to standard technique. The Hardware cosimulation of the design is initial validated and then implemented with Xilinx Virtex-V FPGA.

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