PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash - 2016


With aggressive scaling and multilevel cell technology, the reliability of NAND flash continuously degrades. The lifetime of NAND flash is highly restricted by the bit error rate (BER), and error-correcting codes (ECCs) can provide solely restricted error correction capability to tolerate increasing bit errors. To deal with this issue, a unique page endurance variance aware (PEVA) strategy is proposed to increase the lifetime of NAND flash primarily based on the experimental observations from our hardware-software codesigned experimental platform. The experimental observations indicate that the BER distribution of retention error shows distinct variances in several pages. The key purpose of PEVA is to take advantage of the lifetime potency of each page in an exceedingly block by introducing fine-grained dangerous page management instead of coarse-grained unhealthy block management (BBM). The experimental results show that the PEVA will extend the lifetime of two×-nm NAND flash by 9.8× compared with the conventional BBM and that there is at most an 8.7percent degradation in writing speed compared with the traditional sector mapping technology. In addition, the maximum writing response time increased by at most 5.ninep.c throughout the operation of the PEVA strategy.

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