Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures - 2016

PROJECT TITLE :

Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures - 2016

ABSTRACT:

The coarse-grained reconfigurable architectures (CGRAs) are a promising class of architectures with the advantages of high performance and high power efficiency. The compute-intensive parts of an application (e.g., loops) are often mapped onto the CGRA for acceleration. Due to the extra overhead of memory access and also the restricted Communication bandwidth between the processing component (PE) array and native memory, previous works making an attempt to resolve the routing drawback are mainly confined in the internal resources of PE arrays (e.g., PEs and registers). Inevitably, routing with PEs or registers will consume a heap of computational resources and cause the rise of the initiation interval. To resolve this downside, this paper makes two contributions: 1) establishing a certain formulation for the CGRA mapping drawback whereas using shared native data memory as a routing resource and a couple of) extracting an efficient approach for mapping loops to CGRAs. The experimental results on loops of the SPEC2006, Livermore, and MiBench show that our approach (known as MEMMap) can improve the performance of the kernels on CGRA up to one.sixty two×, 1.58×, one.twenty eight×, and 1.23× compared with the sting-centric modulo scheduling, EPIMap, REGIMap, and force-directed map, respectively, with an appropriate increase in compilation time.

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