Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application - 2016

PROJECT TITLE :

Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application - 2016

ABSTRACT:

During this paper, we present a completely unique channelization architecture, which will simultaneously method 2 channels of advanced input information and provide up to 1024 freelance channels of complicated output data. The proposed design is very modular and generic, therefore that parameters of each output channel will be dynamically changed even at runtime in terms of the bandwidth, center frequency, output sampling rate, and therefore on. It consists of one tunable pipelined frequency transform (TPFT)-based coarse channelization block, one tuning unit, and one resampling filter. Primarily based on the analysis of the data dependence between the subbands, a completely unique channel splitting scheme is proposed to enable multiple subbands to share the proposed TPFT block. The multiplier block (MB) and subexpression sharing techniques are used to reduce the quantity of arithmetic units of the TPFT block. Moreover, the proposed Farrow-primarily based resampling filter does not need division operation and twin-port RAMs ensuing in vital area saving. Finally, we have a tendency to implement the proposed channelization design in an exceedingly single field-programmable gate array. The experiment results indicate that our design provides the flexibility associated with the present works, however with larger resource efficiency.

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