Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic - 2016


Hardware acceleration has been proved an extremely promising implementation strategy for the digital signal processing (DSP) domain. In preference to adopting a monolithic application-specific integrated circuit design approach, in this brief, we have a tendency to present a novel accelerator design comprising flexible computational units that support the execution of a big set of operation templates found in DSP kernels. We have a tendency to differentiate from previous works on versatile accelerators by enabling computations to be aggressively performed with carry-save (CS) formatted knowledge. Advanced arithmetic style ideas, i.e., recoding techniques, are utilised enabling CS optimizations to be performed in an exceedingly larger scope than in previous approaches. Extensive experimental evaluations show that the proposed accelerator design delivers average gains of up to sixty one.91percent in area-delay product and 54.forty three% in energy consumption compared with the state-of-art flexible datapaths.

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