An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells - 2015


An all-digital programmable and reconfigurable stochastic analog-to-digital converter (ADC) is presented during this work. This ADC directly advantages from scaling by using solely digital gates and counting on an increased mismatch between minimum-sized transistors. The programmability and reconfigurability are achieved by dividing the look into eight channels. The mean of every channel is about independently employing a digitally generated analog reference voltage with a ten-bit management word. The output of each channel is linearized using Gaussian linear interpolation. The entire ADC is written in Verilog and synthesized into digital normal cells using regular digital design tools. Fabricated in an exceedingly a hundred thirty-nm complementary metal-oxide-semiconductor process, the ADC covers signal-to-noise and distortion ratio from 28 to thirty four.9 dB with a programmable differential input range of 400-800 mVpp at 140 MS/s and zero.7-V offer.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE : An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop - 2016 ABSTRACT: With increased levels of integration in trendy system-on-chips, the coupling of supply noise in a very phase-locked
PROJECT TITLE : A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register - 2016 ABSTRACT: This transient presents a quick-acquisition 11-bit all-digital
PROJECT TITLE :Guest Editorial Special Issue on the 2015 IEEE International Instrumentation and Measurement Technology Conference Pisa, Italy, May 11–14, 2015ABSTRACT:The thirty second annual IEEE International Instrumentation
PROJECT TITLE :5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memoryABSTRACT:A replacement low-power, fast-locking, all-digital delay-locked loop (DLL)
PROJECT TITLE :A Wide-Range Low-Cost All-Digital Duty-Cycle CorrectorABSTRACT:A system clock with a 50p.c duty cycle is demanded in high-speed information communication applications, such as double data rate recollections and

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry