HMFPCC - Hybrid-mode floating point conversion co-processor - 2015
This research and development on conversion co-processor presents an abstract- level hardware implementation of the conversion between varied variety formats for FPGAs in modular way. Replacing the floating purpose expressions with specialized integer or mounted purpose operations will greatly improve the system performance in several applications. The replacement requires several types of conversions from one format to a different format. The proposed conversion co-processor accelerator will work in parallel with HOST machine to just accept a giant amount of input information and convert to a different format and apply fixed point or integer arithmetic operations and the result is converted back to the floating purpose or fixed point format. The floating point conversions unit designs are totally compliant with the IEEE 754-2008 customary. The proposed system has been tested on Xilinx Virtex half-dozen xc6vlx550t-2ff1759 FPGA and achieves a throughput of 350MFLOPs per second.
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