Design and Analysis of Approximate Compressors for Multiplication - 2015


Inexact (or approximate) computing is an attractive paradigm for digital processing at nanometric scales. Inexact computing is particularly interesting for pc arithmetic designs. This project deals with the analysis and style of 2 new approximate four-a pair of compressors for utilization in a multiplier. These styles depend on completely different features of compression, such that imprecision in computation (as measured by the error rate and the thus-referred to as normalized error distance) will meet with respect to circuit-primarily based figures of benefit of a design (number of transistors, delay and power consumption). Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Dadda multiplier. Extensive simulation results are provided and an application of the approximate multipliers to image processing is presented. The results show that the proposed designs accomplish important reductions in power dissipation, delay and transistor count compared to an exact design; moreover, two of the proposed multiplier designs offer excellent capabilities for image multiplication with respect to average normalized error distance and peak signal-to-noise ratio (additional than 50 dB for the thought-about image examples).

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