Design & Analysis of 16 bit RISC Processor Using low Power Pipelining - 2015
A 16 bit low power pipelined RISC processor is proposed by us during this project, the RISC processor consists of the block mainly ALU, Universal shift register and Barrel Shifter. We tend to have used changed Harvard architecture that uses separate recollections for its instruction & data memory response where as in the other design by von Neumann, has only one shared memory for instruction and data, with one knowledge bus and address bus with between information memory & processor memory. The remedial architectural modification has been made in incremental circuit utilized in carry choose adder unit of the ALU in the RISC Processor. Operation within the core RISC Processor Fetch, Decode, execute, write back is implemented in the 2 stage pipelining with the positive edge & negative Edge. The process has been realized using XILINX ISE Style suit 13.2 & the Dynamic power is minimized within the RISC Core through the clock gating technique that's an economical power technique and the overall power estimation is finished by the X Power analyzer. All the implementation is completed in XILINX KINTEX XC7K1607-3fbg676 in it kit twenty eight nm technology are used. The simulation illustrate the entire power dissipated by the processor to be zero.220 watt, and the Latency is 1.5 cycle.
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