FPGA-Based Bit Error Rate PerformanceMeasurement of Wireless Systems - 2014
This project presents the bit error rate (BER) performance validation of digital baseband communication systems on a field-programmable gate array (FPGA). The proposed BER tester (BERT) integrates basic baseband signal processing modules of a typical wireless communication system together with a sensible fading channel simulator and an accurate Gaussian noise generator onto a single FPGA to produce an accelerated and repeatable take a look at atmosphere during a laboratory setting. Using a developed graphical user interface, the error rate performance of single- and multiple-antenna systems over a big selection of parameters can be rapidly evaluated. The FPGA-based mostly BERT should scale back the need for time-consuming software-primarily based simulations, hence increasing the productivity. This FPGA-based mostly resolution is significantly a lot of price effective than conventional performance measurements created using expensive commercially obtainable check equipment and channel simulators.
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