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FHAST: FPGA-Based Acceleration of Bowtie in Hardware

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PROJECT TITLE :

FHAST: FPGA-Based Acceleration of Bowtie in Hardware

ABSTRACT:

Whereas the sequencing capability of modern instruments continues to extend exponentially, the computational drawback of mapping short sequenced reads to a reference genome still constitutes a bottleneck within the analysis pipeline. A selection of mapping tools (e.g., BOWTIE, BWA) is obtainable for general-purpose computer architectures. These tools can take several hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the quantity of allowed mismatches or insertion/deletions, creating the mapping downside an ideal candidate for hardware acceleration. During this paper, we have a tendency to gift FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for BOWTIE that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism obtainable to us on an FPGA. We tend to have implemented and tested FHAST on the Convey HC-one and later ported on the Convey HC-2ex, taking advantage of the big memory bandwidth offered to those systems and the shared memory image between hardware and software. A preliminary version of FHASTrunning on the Convey HC-one achieved up to seventy× speedup compared to BOWTIE (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to twelve× fold speed gain compared to BOWTIE running eight threads on an eight-core standard architecture, whereas maintaining nearly identical mapping accuracy. FHAST may be a drop-in replacement for BOWTIE, thus it can be incorporated in any analysis pipeline that uses BOWTIE (e.g., TOPHAT).


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FHAST: FPGA-Based Acceleration of Bowtie in Hardware - 4.7 out of 5 based on 94 votes

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