An Efficient Field Programmable Gate ArrayImplementation of Double Precision Floating Point Multiplier using VHDL - 2014


Floating-point numbers are widely adopted in many applications because of their dynamic illustration capabilities. Basically floating point numbers are one attainable manner of representing real numbers in binary format. Multiplying floating point numbers is additionally a important requirement for DSP applications involving large dynamic vary. The IEEE 754 normal presents 2 completely different floating point formats, Binary interchange format and Decimal interchange format. This project presents the floating point multiplier that supports the IEEE 754 binary interchange format. This project mainly focuses on double precision floating point multiplier primarily based on Booth algorithm. The main object of this project is to cut back the facility consumption and to increase the speed of execution by implementing certain algorithm for multiplying 2 floating point numbers. In order to design this, VHDL is employed and targeted on a Xilinx Virtex-five FPGA. The implementation " s tradeoffs are area, speed and power. In this project Shift and Add Multiplier is compared with Radix-four Booth Multiplier. This multiplier additionally handles overflow and underflow cases. For high accuracy of the results normalization is also applied. Floating Point (FP) multiplication is widely employed in massive set of scientific and signal processing computation. Multiplication is one in all the common arithmetic operations in these computations. Conjointly the necessity of high speed multiplier is increasing as the necessity of high speed processors are increasing. Higher throughput arithmetic operations are necessary to attain the desired performance in several real time signal and image processing applications. One amongst the key arithmetic operations in such applications is multiplication and the development of quick multiplier circuit has been a subject matter of interest over decades. Conjointly reducing the time delay and power consumption are terribly essential necessities for many applications. Floating point numbers are one possible way of representing real numbers in binary format. The IEEE has produced a standard to define floating purpose representation and arithmetic that is called IEEE 754 normal and that is the most common illustration nowadays for real numbers on pc. IEEE 754 essentially specifies two formats for representing floating point values. They are single precision and double precision floating point format. This project mainly focuses on double precision floating purpose multiplier. In IEEE-754 double precision binary format, sign (S) is represented with one bit, exponent (E) and fraction (M or Mantissa) are represented with eleven and fifty two bits respectively. For a range is claimed to be a normalized number,

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