PROJECT TITLE:

Design of High Performance 64 bit MAC Unit - 2014

ABSTRACT:

A style of high performance sixty four bit Multiplier-and-Accumulator (MAC) is implemented in this project. MAC unit performs necessary operation in many of the Digital Signal Processing (DSP) applications. The multiplier is meant using changed Wallace multiplier and the adder is finished with carry save adder. The total style is coded with Verilog-HDL and the synthesis is done using Cadence RTL complier using typical libraries of TSMC 0.18um technology. The total MAC unit operates at 217 MHz. The total power dissipation is seventeenseven.732 mW.


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