Design for Testability Support for Launch and Capture Power Reduction in Launch Off Shift and Launch Off Capture Testing - 2014


At-speed or even faster-than-at-speed VLSI circuit testing aims at high-quality circuit screening by targeting performance-related faults. On the one side, it is beneficial to look at costs in a compact test set of highly efficient patterns, each detecting several delay faults. On the other hand, during launch and capture operations, such trends increase switching activity. Quality and value optimized patterns may thus end up breaching peak power constraints, resulting in loss of yield, whereas pattern generation under low limitations of switching operation which lead to losses in looking at inflation of quality and/or pattern count. In this project, we propose support for testability design (DfT) to allow the use of a group of patterns optimized for price and quality, but in an extremely low power way; we tend to build 3 different DfT mechanisms, one for launch-off move, one for launch-off capture, and one for mixed at-speed testing. A design partitioning approach allows the proposed DfT support, where any given set of patterns created in a power-unware manner, will be used to check the piecemeal look regions, reducing both launch and capture power in a style-flow-compatible manner. This way it is possible to maintain the pattern count and quality of the optimized check collection, while lowering the launch/capture capacity.

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