Design for Testability Support for Launch and Capture Power Reduction in Launch Off Shift and Launch Off Capture Testing - 2014


At-speed or maybe faster-than-at-speed testing of VLSI circuits aims for high-quality screening of the circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, every detecting multiple delay faults, is desirable for lower take a look at costs. On the other hand, such patterns increase switching activity throughout launch and capture operations. Patterns optimized for quality and value may so finish up violating peak-power constraints, resulting in yield loss, while pattern generation under low switching activity constraints might lead to loss in take a look at quality and/or pattern count inflation. In this project, we propose design for testability (DfT) support for enabling the utilization of a group of patterns optimized for price and quality as is, however in an exceedingly low power manner; we tend to develop 3 different DfT mechanisms, one for launch-off shift, one for launch-off capture, and one for mixed at-speed testing. The proposed DfT support enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, will be utilized to check the look regions piecemeal, reducing both launch and capture power during a style-flow-compatible manner. This way, the take a look at pattern count and quality of the optimized check set can be preserved, whereas lowering the launch/capture power.

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