Fast Radix 10 Multiplication Using Redundant BCD Codes - 2014


We tend to gift the algorithm and architecture of a BCD parallel multiplier that exploits some properties of 2 totally different redundant BCD codes to speedup its computation: the redundant BCD excess-three code (XS-3), and the overloaded BCD illustration (ODDS). In addition, new techniques are developed to scale back considerably the latency and area of previous representative high-performance implementations. Partial products are generated in parallel employing a signed-digit radix-10 recoding of the BCD multiplier with the digit set [-five, 5], and a group of positive multiplicand multiples (0X, 1X, 2X, 3X, 4X, 5X) coded in XS-3. This encoding has many advantages. 1st, it's a self-complementing code, therefore that a negative multiplicand multiple can be obtained by simply inverting the bits of the corresponding positive one. Additionally, the on the market redundancy allows a fast and simple generation of multiplicand multiples during a carry-free way. Finally, the partial products can be recoded to the ODDS representation by just adding a continuing issue into the partial product reduction tree. Since the ODDS uses an analogous four-bit binary encoding as non-redundant BCD, conventional binary VLSI circuit techniques, like binary carry-save adders and compressor trees, will be tailored efficiently to perform decimal operations. To show the benefits of our design, we tend to have synthesized a RTL model for sixteen×sixteen-digit and thirty four×34-digit multiplications and performed a comparative survey of the previous most representative styles. We have a tendency to show that the proposed decimal multiplier has an area improvement roughly within the range twenty-35 % for similar target delays with respect to the fastest implementation.

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