High Speed Convolution and De convolution Algorithm - 2014


In Digital Signal Processing, the convolution and deconvolution with a terribly long sequence is ubiquitous in several application areas. The basic blocks in convolution and deconvolution implementation are multiplier and divider. They consume much of your time. This project presents a right away methodology of computing the discrete linear convolution, circular convolution and deconvolution. The approach is easy to find out as a result of of the similarities to computing the multiplication of 2 numbers. The foremost vital facet of the proposed methodology is the event of a multiplier and divider design primarily based on Ancient Indian Vedic Arithmetic sutras Urdhvatriyagbhyam and Nikhilam algorithm. The results show that the implementation of linear convolution and circular convolution using vedic mathematics is economical in terms of area and speed compared to their implementation using standard multiplier & divider architectures. The coding is done in VHDL. Simulation and Synthesis are performed using Xilinx ISE style suit 14.a pair of. Simulated results for proposed 4x4 bit Vedic convolution circuit shows a discount in delay of 88percent than the conventional methodology and forty onepercent than the OLA method.

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