Area Delay Efficient Binary Adders in QCA - 2014
As transistors decrease in size additional and a lot of of them will be accommodated in an exceedingly single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one amongst the attainable solutions in overcoming this physical limit, although the planning of logic modules in QCA is not perpetually straightforward. In this temporary, we tend to propose a new adder that outperforms all state-of-the-art competitors and achieves the simplest area-delay tradeoff. The above advantages are obtained by using an overall space like the cheaper designs known in literature. The sixty four-bit version of the novel adder spans over eighteen.72 µa pair of of active space and shows a delay of solely nine clock cycles, that is just thirty six clock phases.
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