The Open Core Protocol (OCP) is a core centric protocol which defines a high-performance, bus-freelance interface between IP cores that reduces design time, style risk, and producing costs for SOC styles. Main property of OCP is that it can be configured with respect to the application needed. The OCP is chosen as a result of of its advanced supporting features like configurable sideband control signaling and take a look at harness signals, compared to different core protocols.
The OCP defines a point-to-purpose interface between two communicating entities like IP cores and bus interface modules. One entity acts because the master of the OCP instance, and the other as the slave. Only the master will present commands and is that the controlling entity. The slave responds to commands presented to it, either by accepting information from the master, or presenting knowledge to the master. For two entities to communicate there want to be 2 instances of the OCP connecting them like one where the first entity is a master and one where the primary entity may be a slave.
In this work, the numerous OCP profiles will be designed using Verilog and the developed design will be used with respect to its appropriate application in the important time product. Basically the OCP unifies all inter-core communications. The OCP’s synchronous unidirectional signaling produces simplified core implementation, integration and timing analysis. The OCP readily adapts to support new core capabilities while limiting check suite modifications for core upgrades.
- This protocol can be configured with respect to the Application which basically reduces the Area (Die Size) and the Design time
- This will provide lossless communication between two IP Cores
- Verilog HDL
- MODELSIM – Simulation
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