Discrete cosine rework (DCT) may be a widely used tool in image and video compression applications. Recently, the high-throughput DCT styles are adopted to fit the necessities of real-time application.
Operating the shifting and addition in parallel, a mistake-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to attain low-error and high-throughput discrete cosine rework (DCT) design. Rather than the 12 bits employed in previous works, 9-bit distributed arithmetic. DA-based DCT core with miscalculation-compensated adder-tree (ECAT). The proposed ECAT operates shifting and addition in parallel by unrolling all the words required to be computed. Furthermore, the error-compensated circuit alleviates the truncation error for top accuracy design. Primarily based on low-error ECAT, the DA-precision during this work is chosen to be 9 bits rather than the traditional 12 bits. Therefore, the hardware value is reduced, and the speed is improved using the proposed ECAT.
- Hardware cost is reduced.
- Speed is improved.
- Image Compression.
- Video Compression
- Verilog HDL.
- Simulation- ModelSim XE III 6.4b.
- Synthesis - XiLinx ISE 10.1.
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