# An Efficient Implementation Of Floating Point Multiplier

ABSTRACTS:

A floating-purpose multiplier is nothing new. The IEEE 754 customary was printed in 1985 and was primarily based on work that was already recent at the time. Why should engineers spend time redesigning the proverbial wheel? Put simply, they should not. But they do, regardless. Engineers pay precious style time on already completed tasks for several reasons. Perhaps they need a multiplier with a 25-bit significant instead of the quality twenty three. Perhaps they need to squeeze the multiplier onto a field programmable gate array with other massive parts, and do not have space to incorporate unneeded options.

All calculations are performed on double precision numbers, therefore if the input operands are in single precision, they have to be converted to double precision. Single-To-Double Conversion Block carries conversion task. After double precision values are obtained, two numbers are checked for predefined special values for which result can be determined instantly, if a case is identified output is generated by special output block. If no case is found operands are split into three parts: sign, exponent and mantissa, and every of them is routed to respective arithmetic block. Mantissa Arithmetic Block task is to multiply 2 53 bit binary numbers (most vital bit is assumed to be 'one'), normalize the result from multiplier, and round normalized worth. It conjointly generates signals foe exponent path to adjust exponent for normalization and rounding overflow, and inexact signal for special case output.

For multiplying operation of floating point numbers, sign, exponent and mantissa half should be handled individually. Because IEEE 754 format (single) of floating point format is adopted here. Thus, every operand has eight-bit exponent and 23-bit mantissa and one-bit sign. To calculate the result, the calculation is composed of

• Single-bit XOR the signs of two operands.
• 8-bit addition of the exponents of 2 operands.
• twenty three-bit multiplication is to be performed to come up with the fraction result.

This is the basic three steps. Some accessories also are required for shift operation and extra eight bit adder or subtractor to adjust the bias of exponent part in IEEE 754 format.

Rounding happens in floating purpose multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. The least important 24 bits are discarded. Overflow occurs when the add of the exponents exceeds 127, the largest worth that is outlined in bias-127 exponent representation. When this happens, the exponent is set to 128 (E = twenty fivefive) and the mantissa is ready to zero indicating + or - infinity. Underflow occurs when the total of the exponents is more negative than -126, the foremost negative value that is defined in bias-127 exponent illustration. When this occurs, the exponent is about to -127 (E = zero). If M = zero, the quantity is exactly zero. If M is not zero, then a de-normalized range is indicated which has a devotee of -127 and a hidden little bit of 0. The smallest such range that isn't zero is a pair of-149. This range retains only a single little bit of precision within the rightmost little bit of the mantissa.

APPLICATIONS:

• Math coprocessors
• DSP algorithms
• Embedded arithmetic coprocessor
• Data processing & control

TOOLS REQUIRED:

• MODELSIM – Simulation,
• XILINX-ISE – Synthesis

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