PROJECT TITLE:

Design and Estimation of delay power and area for Parallel prefix adders - 2014

ABSTRACT:

In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance. This project investigates four varieties of PPA's (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)). Additionally Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated. These adders are implemented in Verilog Hardware Description Language (HDL) using Xilinx Integrated Software Atmosphere (ISE) thirteen.2 Design Suite. These designs are implemented in Xilinx Virtex five Field Programmable Gate Arrays (FPGA) and delays are measured using Agilent 1692A logic analyzer and all these adder's delay, power and area are investigated and compared finally.