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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. A Low-Complexity Multiple Error CorrectingArchitecture Using Novel Cross ParityCodes Over GF(2m). - 2015
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Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
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A Low-Complexity Multiple Error CorrectingArchitecture Using Novel Cross ParityCodes Over GF(2m). - 2015

PROJECT TITLE:

A Low-Complexity Multiple Error CorrectingArchitecture Using Novel Cross ParityCodes Over GF(2m). - 2015

ABSTRACT:

This project presents a unique low-complexity cross parity code, with a wide range of multiple bit error correction capability at a lower overhead, for improving the reliability in circuits over GF(2m). For an m input circuit, the proposed theme can correct m = Dw = 3m/2 -1 multiple error combinations out of all the possible 2m - 1 errors, that is superior to several existing approaches. From the mathematical and practical evaluations, the most effective case error correction is m/a pair of bit errors. Tests on eighty-bit parallel and, for the primary time, on 163-bit Federal Info Processing Normal/National Institute of Standards and Technology (FIPS/NIST) standard word-level Galois field (GF) multipliers, recommend that it needs solely 106% and a hundred and seventypercent space overheads, respectively, which is under the present approaches, whereas error injection-primarily based behavioral analysis demonstrates its wider error correction capability.

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Previous article: Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic - 2015 Aging-Aware Reliable Multiplier Design WithAdaptive Hold Logic - 2015 Next article: A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications - 2016 A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications - 2016
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