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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. A Method to Extend Orthogonal Latin Square Codes - 2014
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Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
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A Method to Extend Orthogonal Latin Square Codes - 2014

PROJECT TITLE:

A Method to Extend Orthogonal Latin Square Codes - 2014

ABSTRACT:

Error correction codes (ECCs) are commonly used to safeguard recollections from errors. As multibit errors become more frequent, single error correction codes don't seem to be enough and more advanced ECCs are needed. The use of advanced ECCs in recollections is, however, restricted by their decoding complexity. In this context, one-step majority logic decodable (OS-MLD) codes are an fascinating choice because the decoding is straightforward and can be implemented with low delay. Orthogonal Latin squares (OLS) codes are OS-MLD and are recently thought-about to guard caches and recollections. The main advantage of OLS codes is that they supply a wide selection of choices for the block size and the error correction capabilities. In this transient, a technique to extend OLS codes is presented. The proposed methodology enables the extension of the info block size which will be protected with a given variety of parity bits so reducing the overhead. The extended codes are OS-MLD and have the same decoding complexity to that of the initial OLS codes. The proposed codes have been implemented to guage the circuit area and delay required for various block sizes.

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