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  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells - 2015
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Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
Hits: 56

An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells - 2015

PROJECT TITLE:

An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells - 2015

ABSTRACT:

An all-digital programmable and reconfigurable stochastic analog-to-digital converter (ADC) is presented during this work. This ADC directly advantages from scaling by using solely digital gates and counting on an increased mismatch between minimum-sized transistors. The programmability and reconfigurability are achieved by dividing the look into eight channels. The mean of every channel is about independently employing a digitally generated analog reference voltage with a ten-bit management word. The output of each channel is linearized using Gaussian linear interpolation. The entire ADC is written in Verilog and synthesized into digital normal cells using regular digital design tools. Fabricated in an exceedingly a hundred thirty-nm complementary metal-oxide-semiconductor process, the ADC covers signal-to-noise and distortion ratio from 28 to thirty four.9 dB with a programmable differential input range of 400-800 mVpp at 140 MS/s and zero.7-V offer.

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