PROJECT TITLE:

Reverse Converter Design via Parallel Prefix Adders Novel Components Methodology and Implementations - 2014

ABSTRACT:

In this brief, the implementation of residue number system reverse converters primarily based on well-known regular and modular parallel-prefix adders is analyzed. The VLSI implementation results show a important delay reduction and space × time2 enhancements, all this at the price of higher power consumption, which is the main reason preventing the use of parallel-prefix adders to realize high-speed reverse converters in these days systems. Hence, to unravel the high power consumption downside, novel specific hybrid parallel-prefix-based mostly adder elements that offer higher tradeoff between delay and power consumption are herein presented to design reverse converters. A methodology is also described to style reverse converters based on totally different sorts of prefix adders. This methodology helps the designer to adjust the performance of the reverse converter based on the target application and existing constraints.