PROJECT TITLE:

Read Performance The Newest Barrier in Scaled STT-RAM - 2015

ABSTRACT:

Spin-torque transfer RAM (STT-RAM), a promising different to static RAM (SRAM) for reducing leakage power consumption, has been widely studied to mitigate the impact of its asymmetrically long write latency. However, physical effects of technology scaling all the way down to forty five nm and below, in explicit, method variation, introduce the previously unreported and alarming trends in scan performance and reliability due to reduced sensing margins and increasing error rates. During this transient, we tend to study the scaling trends of STT-RAM from sixty five right down to 22 nm as they pertain to scan performance, including a 50percent increase in sensing versus peripheral circuit delay ratio and a more than eighty% increase in uncorrectable scan error rates. Through differential sensing, we have a tendency to show how 22 nm will return to sense delay ratio levels at 65 nm and uncorrectable browse errors will be reduced by an order of magnitude. Through a case study of a multilevel STT-RAM cache, we show how a reconfigurable cache cell will produce an extreme access mode (X-mode) based mostly on differential sensing improve to outperform the state-of-the-art STT-RAM caching techniques in each raw performance and performance per watt by additional than ten% whereas still reducing energy consumption over SRAM caches by additional than one/three.