A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning - 2015

PROJECT TITLE:

A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning - 2015

ABSTRACT:

Clock skew minimization that's an vital issue in very massive scale integration style has become troublesome thanks to the presence of method, voltage, and temperature (PVT) variations. The post-silicon skew tuning (PST) technique with the ability to tolerate PVT variations, even when a chip is manufactured has generated considerable discussion. The basic idea of the PST architecture is to reduce the clock skew dynamically. Unlike most previous works that have focused on the implementation and therefore the performance problems of a PST architecture, this project focuses on the testing problems of a PST design. But, testing the variation tolerance ability of the PST design is troublesome because the clock skew will ultimately have an effect on the functionality of a style. In this project, we have a tendency to propose an efficient fault model considering the physical limitation of the devices for the PST design. As well, we have a tendency to propose some novel structures to detect the manufacturing faults and increase the robustness of a PST design. Our experiment shows that with a little increase in overhead, we tend to will achieve robustness.

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