Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks - 2016 PROJECT TITLE: Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks - 2016 ABSTRACT: Soft errors cause a reliability threat to modern electronic circuits. This makes protection against soft errors a requirement for several applications. Communications and Signal Processing systems aren't any exceptions to the present trend. For some applications, an interesting possibility is to use algorithmic-primarily based fault tolerance (ABFT) techniques that try to use the algorithmic properties to detect and proper errors. Signal Processing and Communication applications are well fitted to ABFT. One example is quick Fourier transforms (FFTs) that are a key building block in many systems. Many protection schemes are proposed to detect and proper errors in FFTs. Among those, most likely the use of the Parseval or sum of squares check is the most widely known. In modern Communication systems, it is increasingly common to find several blocks operating in parallel. Recently, a way that exploits this fact to implement fault tolerance on parallel filters has been proposed. In this temporary, this technique is 1st applied to guard FFTs. Then, 2 improved protection schemes that mix the employment of error correction codes and Parseval checks are proposed and evaluated. The results show that the proposed schemes can more reduce the implementation value of protection. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A novel VHDL implementation of UART with single error correction and double error detection capability - 2015 Fault Tolerant Parallel Filters Based on Error Correction Codes - 2015
