Implementation of Sub-threshold AdiabaticLogic for Ultralow-Power Application - 2016

PROJECT TITLE:

Implementation of Sub-threshold AdiabaticLogic for Ultralow-Power Application - 2016

ABSTRACT:

Adiabatic logic circuits in weak inversion region or sub threshold region is calculated in deepness for the first time in the reporting to make great improvement in ultra low power circuit style. Adiabatic Logic circuits are operated with an oscillating power supply. The sub-threshold adiabatic logic for VLSI circuits primarily based on power delay product. The voltage scaling methodology was used to scale back the facility consumption. The sub threshold adiabatic units can save significant energy compared with a logically equivalent static CMOS implementation. The 8T static random access memory was designed and additionally improved both read and write stability in sub threshold region for ultra low power applications. The propose scheme uses a 3T gain cell (GC) dynamic random access memory (DRAM) bit cell that operates with one-provide voltage and provides additional write capability to the predictable GC structures. The propose GC is operated from a single supply voltage, eliminating the boosted voltages. The propose circuit is targeted at low power energy economical applications. In the propose scheme area can be reduced as compared with the 8T static random access memory. By using TINA and MICROWIND simulator the power consumption and space can be reduced.

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