On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays - 2014

PROJECT TITLE:

On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays - 2014

ABSTRACT:

Often, when performing mounted-purpose multiplication, it's sufficient to return a faithfully rounded result, i.e., the machine representable variety either immediately above or below the arbitrary precision result, if the latter is not exactly representable. Compared to correctly rounded multipliers, i.e., those returning the closest machine representable variety, faithfully rounded multipliers use significantly less silicon space, sometimes by implementing a truncation theme among the partial product array. A range of such heuristically inspired schemes exist in the literature, but their use in industrial apply is hampered by the absence of verification, and exhaustive simulation is usually infeasible, e.g., a 32 bit multiplier requires 264 simulations. We have a tendency to present 3 truncated multiplier schemes that subsume the bulk of existing schemes and derive both closed kind necessary and sufficient conditions for devoted rounding. For 2 of the schemes we provide closed type expressions for the bit vectors giving rise to the worst-case error and therefore the likelihood of encountering these inputs throughout Monte-Carlo simulation. From these expressions, we show how HDL code can be created that performs correct-by-construction faithfully rounded multiplication. We have a tendency to also present a method for truncating an arbitrary array while maintaining trustworthy rounding, creating two novel truncated multiplier schemes in the method.

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