Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers PROJECT TITLE :Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting PredriversABSTRACT: This paper investigates the performance of the interconnects with repeater insertion within the subthreshold region. A 3X complementary metal–oxide–semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the standard repeater, the proposed ones have higher energy efficiency. Yet, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration underneath the method and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for ten-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS method. The measured results show that the 3X (4X) predrivers will achieve 5 Mb/s (one.5 Mb/s) knowledge rate at zero.fifteen V with an potency of thirty five.2 fJ (32.8 fJ). Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Using Transmission Lines for Global On-Chip Communication Swizzle-Switch Networks for Many-Core Systems
