PROJECT TITLE :
The demand for capability and off-chip bandwidth to dynamic random-access memory (DRAM) will continue to grow as we integrate more cores onto a die. But, as the info rate of DRAM has increased, the number of twin in-line memory modules (DIMMs) supported on a multi-drop bus has decreased. Therefore, ancient memory systems don't seem to be sufficient to meet each these demands. We propose the DIMM tree design for better scalability by connecting the DIMMs as a tree. The DIMM tree architecture is in a position to grow the amount of DIMMs exponentially with every level of latency in the tree. We also propose application of multiband radio-frequency interconnect (MRF-I) to the DIMM tree architecture for even larger scalability and higher throughput. The DIMM tree architecture without MRF-I was in a position to scale up to sixty four DIMMs with only an eightpercent degradation in throughput over an ideal system. The DIMM tree design with MRF-I was ready to extend throughput by sixty eight% (up to two hundred%) on a 64-DIMM system over a 4-DIMM system. Finally, we propose the partitioned DIMM tree, that allows the scaling of a main memory system to a many-DIMM memory system while still maintaining high throughput. The partitioned DIMM tree is in a position to boost throughput by a median of 19p.c up to thirty fivep.c over the DIMM tree with 256 DIMMs on one channel.
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