PROJECT TITLE :
The continuing scaling of transistors has increased the number of cores on the market in current processors, and the amount of cores is anticipated to continue to extend. In such manycore processors, the communication between cores with the on-chip interconnect is becoming a challenge because it not solely should offer low latency and high bandwidth however also desires to be cost-effective in terms of power consumption. The communication challenge is not solely within a single chip however providing high bandwidth to the increasing variety of cores from off-chip memory is additionally a challenge. The conventional metal interconnect is restricted, particularly for world communication, and will not scale efficiently. During this paper, we investigate different interconnect technologies that can be exploited to deal with the communication challenges in future manycore processor. We give an overview of the various technologies that are accessible and then, investigate how these interconnect technologies impact the design of the on-chip communication and therefore the system style.
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