PROJECT TITLE :
Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology
This transient deals with a brand new style of low-power SRAM wordline decoder in the 28-nm ultrathin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology. The proposed approach synergistically adopts the poly biasing technique together with single-well/flip-well configurations and body biasing to opportunely tune the brink voltage of the devices within the standby and active mode. A tuning methodology is described to optimize the static energy consumption. Post-layout simulations, done at power supply voltages ranging between one V and 0.five V, have shown that, in comparison with the state-of-the-art techniques based on the identical UTBB FDSOI technology, the proposed style achieves a maximum leakage up to 85% lower without paying significant delay penalties.
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