PROJECT TITLE :
A High-Throughput Low-Complexity Radix- - - FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems
This temporary presents a high-throughput low-complexity 512-point fast Fourier transform (FFT)/inverse fast Fourier remodel (IFFT) processor for IEEE 802.11ad standard aiming at the wireless personal space network applications. To cut back the complexity of twiddle issue multiplication, the radix- - - FFT algorithm is devised. To achieve the throughput of 1.76 GS/s (that is normalized as eight samples/clock) and meet the frame format of single carrier as well as orthogonal frequency division multiplexing physical layer that no interval is inserted between any two 512-length data blocks in a frame, the mixed-radix multipath delay feedback structure is adopted to support the continual information flow. Moreover, we have a tendency to propose a completely unique reorder theme to support parallel normal-order output data flow continuously, which demands only one-RAM-group, i.e., 512-word memory size with terribly simple control logic. Overall, the full FFT/IFFT processor is high throughput and space efficient, and the back-finish simulation results show that the core area of the FFT processor is 1.69 in Silterra zero.thirteen m process.
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