Design of a novel energy efficient topology for maximum magnitude generator


A unique combinational digital device for finding maximum magnitude among the 'n' input numbers is proposed. This most magnitude generator (MaxMG) generates maximum magnitude as an output by utilising the little by little approach from multiple input (multi-bit) values simultaneously. MaxMG generates output from most significant bit (MSB) to least important bit (LSB) in parallel, which utilises a minimum range of gate counts among the multi-bit of multiple input values. The minimum magnitude generator is additionally derived by applying the twin operate to the MaxMG. The proposed design is implemented using Synopsys 90 nm generic library and RTL is written using Verilog HDL. The performance of the proposed style is compared with a rank based Kth max choice algorithm, a parallel tree primarily based most generator utilised comparator-multiplexer combination, an array-primarily based most finder (AB) and improved quad tree (IQT). The little by little parallel processing at the inputs - from MSB to LSB, and the straightforward design utilising a minimum range of gates, makes the proposed style a lot of energy efficient when compared with the Kth max algorithm, the tree primarily based most finder, the AB based mostly most finder, and also the IQT architecture.

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