Area and power efficient decimal carry-free adder


As decimal floating-purpose (DFP) is better than binary floating-point in industrial and money computing as well as billing systems, currency conversion, tax calculation and banking, several analysis activities have been centered on improving the performance of the DFP arithmetic unit recently. To attain the high performance of the DFP arithmetic unit, a fast decimal mounted-point adder is the foremost important building block. The traditional three steps carry-free signed digit (SD) addition algorithm is 1st investigated. A replacement methodology for the decimal SD addition and subtraction based on the digit set [−nine, nine] is proposed. Additionally, a digit-set converter which can directly generate absolutely the value of the result's proposed. A model of the proposed decimal SD adder is implemented in VHDL. Once exhaustive tests to make sure the correctness, the proposed style was synthesised in STM 90 nm technology. The results show that the proposed adder has a lower power and space consumption compared with previous styles.

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