PROJECT TITLE :

Tombstone Initiation Model for Small Form-Factor Surface Mount Passives

ABSTRACT:

Passive parts like capacitors are shrinking in size in electrical systems in tandem with the device transistor options. With the dimensions shrink comes an increased risk of method-induced defects like capacitor tombstoning or billboarding. These defects involve poor connectivity of capacitor terminations to the substrates, affecting the electrical performance of the system. We tend to have developed an analytical model to predict the probability of such defects to occur as a function of the look and process factors. The model demonstrates that the surface tension at part terminals dominates over the inertia forces (component weight) in case of parts with submilligram weight. Bulkier capacitors have lower risk of tombstoning compared to the lighter ones. The analysis conjointly points to alternative modulating factors like element termination width, component height, solder pad size, and the solder paste volume. We have a tendency to conjointly gift the experimental results on small form-factor components that confirm a number of the predictions for the model. Optimum style guidelines for the electrical systems with soldered components can be obtained from this model.