Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs


Adders are the most basic arithmetic units, and usually on the timing crucial methods of microprocessors. Among varied adder configurations, parallel prefix adders provide the simplest performance vs. power/area trade-off, particularly for higher bit-widths. With aggressive technology scaling, the performance of a parallel prefix adder, additionally to the dependence on the logic-level, is set by wire-length and congestion which will be mitigated by adjusting fan-out. This paper proposes a polynomial-time algorithm to synthesize bit parallel prefix adders targeting the minimization of the dimensions of the prefix graph with logic level and any arbitrary fan-out restriction. A structure aware prefix node cloning is then applied to the resultant prefix adder solutions to more optimize the scale of the prefix graphs. The design area exploration by our approach provides a group of pareto-optimal solutions for delay vs. power trade-off, and these pareto-optimal solutions can be employed in high-performance designs instead of choosing from a fastened library (Kogge–Stone, Sklansky, etc.). Experimental results demonstrate that our approach: 1) excels highly competitive business commonplace Synopsys design compiler adder, regular adders such as Sklansky adder and Kogge–Stone adder, and a highly run-time/memory intensive recent algorithm in thirty two nm technology node and a couple of) improves performance/area over even sixty four bit bespoke adders targeting twenty two nm technology library and implemented in an industrial high-performance style.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE : ESVSSE Enabling Efficient, Secure, Verifiable Searchable Symmetric Encryption ABSTRACT: It is believed that symmetric searchable encryption, also known as SSE, will solve the problem of privacy in data outsourcing
PROJECT TITLE :Space-Efficient Verifiable Secret Sharing Using Polynomial Interpolation - 2018ABSTRACT:Preserving information confidentiality in clouds may be a key issue. Secret Sharing, a cryptographic primitive for the distribution
PROJECT TITLE :Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique - 2017ABSTRACT:In CMOS-based application-specific integrated circuit (ASIC) designs, total power consumption
PROJECT TITLE :Maximum Power Point Tracking Control of Photovoltaic Systems: A Polynomial Fuzzy Model-Based Approach - 2017ABSTRACT:This paper introduces a polynomial fuzzy model (PFM)-primarily based maximum power purpose tracking
PROJECT TITLE : Depth Reconstruction From Sparse Samples: Representation, Algorithm, and Sampling - 2015 ABSTRACT: The fast development of 3D technology and computer vision applications has motivated a thrust of methodologies

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry