PROJECT TITLE :
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
Adders are the most basic arithmetic units, and usually on the timing crucial methods of microprocessors. Among varied adder configurations, parallel prefix adders provide the simplest performance vs. power/area trade-off, particularly for higher bit-widths. With aggressive technology scaling, the performance of a parallel prefix adder, additionally to the dependence on the logic-level, is set by wire-length and congestion which will be mitigated by adjusting fan-out. This paper proposes a polynomial-time algorithm to synthesize bit parallel prefix adders targeting the minimization of the dimensions of the prefix graph with logic level and any arbitrary fan-out restriction. A structure aware prefix node cloning is then applied to the resultant prefix adder solutions to more optimize the scale of the prefix graphs. The design area exploration by our approach provides a group of pareto-optimal solutions for delay vs. power trade-off, and these pareto-optimal solutions can be employed in high-performance designs instead of choosing from a fastened library (Kogge–Stone, Sklansky, etc.). Experimental results demonstrate that our approach: 1) excels highly competitive business commonplace Synopsys design compiler adder, regular adders such as Sklansky adder and Kogge–Stone adder, and a highly run-time/memory intensive recent algorithm in thirty two nm technology node and a couple of) improves performance/area over even sixty four bit bespoke adders targeting twenty two nm technology library and implemented in an industrial high-performance style.
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