An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS

PROJECT TITLE :

An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS

ABSTRACT:

As the data rate has been increased over ten Gb/s with copper interconnect, the intersymbol interference (ISI) caused from the channel loss ought to be compensated. While a decision feedback equalizer (DFE), that is widely utilized in the receiver will compensate the ISI, its ability to enhance the signal-to-noise ratio (SNR) is restricted especially for top frequency data patterns (alternating information patterns). Even a DFE with a large range of faucets, that has powerful compensation capability for ISI, can improve only restricted amount of SNR. To improve SNR, this transient presents a one/4th baud-rate continuous-time linear equalizer (CTLE) and a two-tap DFE. The one/fourth baud-rate CTLE recovers data to be adequate for the DFE, and remaining ISI is removed by the DFE. To boost the high frequency gain of the DFE, exclusive or merged adders are introduced, so the proposed equalizer is additional tolerant against channel noise. It compensates 21.seven-dB channel loss and operates with eleven.5-Gb/s information rate because it consumes twenty five.35 mW from one.3 V offer during a 110-nm CMOS technology.

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