Low memory visual saliency architecture for data reduction in wireless sensor networks


Traditionally, to scale back Communication overheads because of bandwidth limitations in wireless sensor networks (WSNs), image compression techniques are used on high-resolution captures. Higher information reduction rates will be achieved by initial removing redundant elements of the capture previous to the application of image compression. To find these redundant parts, biologically plausible visual saliency processing is employed to isolate parts that appeared necessary based mostly on visual perception. Though visual saliency proves to be a good methodology in providing a distinctive distinction between necessary and unimportant regions, computational complexity and memory needs usually impair implementation. This study presents an implementation of an occasional-memory visual saliency architecture with reduced computation complexity for knowledge reduction in WSNs through salient patch transmission. A custom softcore microprocessor-based mostly hardware implementation on a field programmable gate array is then used to verify the architecture. Real-time processing demonstrated that data reductions of more than fiftyp.c are achievable for straightforward to medium scenes while not the appliance of image compression techniques.

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