PROJECT TITLE :

Design and Implementation of Time and Frequency Synchronization in LTE

ABSTRACT:

A unique architecture for efficient time and frequency synchronization, applied to the long-term evolution (LTE) standard, is proposed. For image timing, we tend to propose applying a symbol-folding methodology on top of the sign-bit reduction technique, leading to a completely unique algorithm for the cyclic prefix-type recognition in LTE. Following the symbol timing, the fractional carrier frequency offset is estimated and compensated using an adaptive gain loop, that allows for a high-accuracy compensation in an exceedingly short interval. Within the frequency domain, for cell search, we propose a sign-bit reduction technique on top of the matched filter method for the first synchronization signal detection. In addition, we propose the sign-bit most-probability sequence detection algorithm for the secondary synchronization signal analysis. These methods end in >ninety% hardware reduction within the cell search compared with the state-of-the-art style. Moreover, potential structures for the frequency tracking in LTE are investigated resulting in an experimental comparison, used to choose the simplest hardware-economical structure. The proposed design is fabricated in an exceedingly a hundred thirty-nm CMOS technology occupying 0.sixty eight of silicon area. At twenty five °C and one.2 V provide voltage, the fabricated chip consumes thirty four.four mW at 42 MHz within the time domain and thirty four.half-dozen mW at 188 MHz in the frequency domain. The fabricated and tested synchronizer core proves to own an impressive performance for all defined communication modes in LTE.